With increasingly scaling of integrated circuits (IC's), contacts between respective layers of IC chips are becoming smaller and smaller. However, conventional processes have many problems in fabricating the contacts whose size is increasingly reduced. For example, in order to etch a small contact hole through a dielectric layer, a high bias is required for the reactive ion etching (RIE), which, however, results in a reduced etching selectivity in the RIE of the contact hole. In such a case, the RIE either causes an under-etching of the dielectric layer (with a low RIE bias), or an over-etching of the dielectric layer (with a high RIE bias).
In order to solve the problem, reference 1 (US 2009/0072400 A1) discloses a process of fabricating a contact in two parts. Specifically, the contact comprises two parts: a lower contact and an upper contact. First, the lower contact is formed in a first dielectric layer; and then, the upper contact is formed in a second dielectric layer on the first dielectric layer. The lower and upper contacts are aligned with and electrically connected to each other, so as to constitute a complete contact. In this way, by forming the contact in two steps, the difficulty in etching the contact hole in a single step is significantly reduced.
However, in the above process, the fabrication of the lower contact relies on the photolithography, which has strict requirements on the overlay and critical size of the contact hole. Otherwise, the gate and the source/drain contacts are very likely to be shorted. Accordingly, there is a need for a novel semiconductor device and a method of fabricating the same to overcome the problems of the prior art.